1. Field of the Invention
This invention relates to a semiconductor device having a semiconductor memory circuit whose operation is tested in combination with an external test means, a layout of the semiconductor device and a method of testing the semiconductor memory circuit.
2. Description of the Related Art
A built-in self test (hereinafter called "BIST") has been known as a test on the operation of a semiconductor device. As references about the BIST, there have been disclosed the following ones: (1) "A 45 ns 64 Mb DRAM with a Merged Match-line Test Architecture", S. Mori et al, IEEE, Dige. of Tech. Papers, P. 110-111, 1991, (2) "Design and Test on Computer", by H. Fujiwara, issued by Engineering book publisher, P204-208, and (3) "55 ns 16 Mb DRAM provided with a Self-Test Function", Koike et al, Singaku Giho SDM69-39, P79-85, 1999, etc.
Further, "A zero-Overhead Self-Timed 160 ns 546 CMOS Divider" Williams, T. E. et al, ISSCC, Dig. of Tech. Papers, P98-99, 1991 has been disclosed as a reference about a method of controlling a FIFO (First-In First-Out) circuit related to a test.
In the prior art typified by the above-described disclosures, however, since the amount of transfer of data between a semiconductor device and an external test means increases with a great increase in the capacity of a memory portion of a semiconductor memory circuit, the time required to test the semiconductor memory circuit becomes longer. An increase in the rate of compression of data is also considered as a method of reducing the amount of transfer of the data therebetween. It is however understood from the result of a test based on compressed data that only the test for making a decision as to whether the compressed data is good or bad for each unit of the compressed data, can be realized. It is thus difficult to specify positions where defective data are produced. This will exert an influence on the relief of redundancy of the semiconductor memory circuit having large capacity.
Namely, the relief of its redundancy is intended for the improvement in yield by the replacement of a defective memory cell with a spare memory cell for its relief. However, the non-pinpointing or determination of the position of the defective memory cell will make it difficult to carry out the redundancy relief or will cause needless usage of a memory cell used for the relief of its redundancy because the redundancy relief is performed for each large-scale unit.